The present invention pertains to the field of integrated circuit (IC) design. More particularly, this invention relates to the art of designing deep submicron ICs.
Since the advent of the integrated circuit (IC), circuit components have become smaller and smaller. An IC may include millions of components packed into an incredibly small package. With each new generation of smaller integration, more functionality, and therefore more value, can be derived from ICs. Reliably manufacturing these highly integrated ICs, however, presents significant design challenges.
Those skilled in the art will be familiar with numerous processes for manufacturing ICs. For example, most ICs being with a silicon wafer, and transistors are built one layer at a time in the silicon through repeated applications of photo exposure and chemical processing. A single iteration of the exemplary process usually begins by growing a layer of oxide on the wafer. Then, a layer of light-sensitive material called xe2x80x9cphotoresistxe2x80x9d or xe2x80x9cresistxe2x80x9d is applied to the oxide. A light source exposes areas of the resist either by projecting an image on the resist material through a reticle or by shining through openings in a contact mask. Hereinafter, the term xe2x80x9cmaskxe2x80x9d will be used to generically refer to a contact mask or a reticle.
A chemical process either etches away the exposed resist material or hardens the exposed resist material and etches away the unexposed material to leave behind a layout. Another chemical process transfers the layout from the resist material to the oxide layer to create barriers of oxide protecting the silicon below. Then, the unprotected silicon can be processed in any number of ways, such as electron diffusion or implantation, to create, for instance, p-type or n-type transistor regions.
The remaining oxide can be stripped away and a new layer grown to begin the next layer. A typical IC may require 16 to 24 iterations of photo exposure and chemical processing to build transistors, contact pads, transmission paths, etc.
Manufacturing challenges tend to arise when critical dimensions (the minimum distance between edges of various types of features in various regions in the IC design) approach, or drop below, the wavelength of the light source used to expose the resist. At critical dimensions near or below the light wavelength, typically in the deep submicron range, manufacturing reliability (yield rate) may be affected by several factors including optical proximity distortions and chemical processing fluctuations. Typical problems include line-end pullback and line-width variations that depend on the local pattern density and topology.
FIG. 1A illustrates a simple example of features that may appear on one layer of an IC design. A mask for the design may allow light to pass through the white areas so that the darkened areas are left unexposed. FIG. 1B, however, shows the resulting design in silicon with a deep submicron critical dimension (CD). In many places, not enough light passed through the mask to adequately expose the resist, causing the features to overlap. In deep submicron ICs, whether or not features overlap at a particular point does not depend solely on the distance between the features. For instance, gap 110A and gap 120A have the same width, CD. In FIG. 1B however, corresponding gap 110B does not overlap, but corresponding gap 120B does overlap. Even though both gaps have the same width in the mask, the proximity of edges near gap 120B alters the edge intensity gradient, reducing the intensity of light reaching the resist and causing variations in the chemical processing. Proximity distortions, such as those illustrated in FIG. 1B, can reduce operating speed, or prevent operation entirely, due to breaks in connectivity and short circuits.
Those skilled in the art will be familiar with the term optical proximity correction, or OPC, which generally refers to modifying integrated circuit (IC) designs to compensate for manufacturing distortions due to the relative proximity of edges in the design. As used herein however, OPC may refer to design modifications based not only on the relative proximity of edges, but also on distortions introduced during chemical processing, such as resist etching and oxide etching. Therefore, OPC, as used herein, refers to optical and process correction, and includes design alterations made to improve manufacturability from exposure through chemical processing.
As IC designs become more complex, manual OPC (entering corrections by hand through trial and error) becomes more time consuming and less cost effective. Software modeling, or simulation, is a basis for one form of automated OPC referred to herein as model-based OPC. In model-based OPC, manufacturing distortions can be predicted and compensated for at the design stage by operating on edge fragments. FIG. 2A illustrates a compensated design based on the design of FIG. 1A.
Model-based OPC can be very computationally intensive. For every edge, or fragment of an edge, an edge placement error is determined by simulation. Based on an edge placement error, an edge fragment may be pushed or pulled in an attempt to compensate for the error. The simulations and adjustments may need to be repeated several times for each edge fragment before the edge placement error is within acceptable limits. FIG. 2B illustrates the design in silicon based on the compensated mask.
Another automated approach is referred to herein as rule-based OPC. According to a rule-based approach, whenever a particular feature is encountered, a predetermined alteration is introduced. For instance, at every convex right angle, a xe2x80x9cserifxe2x80x9d can be added, which is basically involves pushing the comer edge fragments out a predetermined distance.
Rule-based OPC, however, relies on the presumption that altering a particular feature with a predetermined change will improve the quality of the manufactured design. The presumption does not always hold true. For instance, in FIG. 2A, not all of the convex right angle edge fragments are pushed out, and of those that are pushed out, they are not all pushed the same distance.
FIG. 3A illustrates another type of IC design feature that is often distorted when manufactured with critical dimensions (CD) near or below the light source wavelength. Densely packed edges alter edge intensity gradients so that edge placement is distorted. Feature 310A extends from a densely packed region to an isolated region. FIG. 3B illustrates what may result. Line width variations, such as the variation over the length of feature 310B, can cause significant problems.
As discussed in U.S. Pat. No. 5,242,770 issued to Chen et al., line width variations can be reduced by employing assist features called leveling bars. FIG. 4 illustrates a set of leveling bars 410. The width W of the leveling bars is too narrow for the features to be reproduced in the resist. According to the ""770 patent, however, leveling bars spaced at a predetermined distance D on either side of the distorted feature should reduce edge placement distortion. In which case, leveling bars can be automatically placed at a predetermined distance D on either side of features such as feature 310A using a rule-based approach.
Model-based OPC, although usually much slower than rule-based OPC, is much more accurate and produces superior yield rates. Rule-based OPC can be faster than model-based OPC because rule-based OPC is less computationally intensive. In which case, using rule-based or model-based OPC is a tradeoff between speed and accuracy.
Thus, it would be desirable if rule-based and model-based OPC could be selectively employed at a feature level in an efficient manner.
The present invention beneficially provides an improved method and apparatus for designing submicron integrated circuits. A tag identifier is provided to an integrated circuit (IC) design. The tag identifier defines a set of properties for edge fragments. Edge fragments are tagged if they have the set of properties defined by the tag identifier. For instance, tag identifiers may define edge fragments that make up line ends or comers, or tag identifiers may define edge fragments that have predetermined edge placement errors.
In various embodiments, functions can be performed on the tagged edge fragments. For instance, rule-based optical and process correction (OPC) or model-based OPC can be performed on the tagged edge fragments. Other functions may mark tagged edge fragments in a visual display of the IC design, display the number of edge fragments having particular tags in a histogram, or identify particularly complex and error prone regions in the IC design.